1. Field of the Invention
This invention relates to an interpolation circuit performing digital interpolation processing to two-phase sinusoidal signals of an encoder, which detects position, angle, velocity, angular velocity and so on, to obtain phase angle data with high resolution.
2. Related Art
Since there is a machining limit in grid spaces formed in a scale of the encoder, a space period of the sinusoidal signals from the encoder should be subdivided to be interpolated in order to measure a space finer than the scale grid. Therefore, various interpolation circuits have been used previously.
FIG. 4 is an example of the interpolation circuit by previous digital processing. Two-phase sinusoidal signals INA and INB of a phase A and a phase B shifted by 90.degree. each other are output from an encoder 1, and then sampled with a predetermined frequency by A/D converters 2a and 2b to be converted to digital data DA and DB respectively. Phase angle data at each sampling point are prepared and stored in a look-up table memory 3 in advance using an arc tangent function (ATAN) based on the following formula. EQU u=ATAN (DB/DA) (1)
Therefore, the phase angle data u at each sampling point is obtained by reading the look-up table memory 3, defining the digital data DA and DB as addresses x and y respectively. Furthermore, the phase angle data u is entered in a two-phase square wave data generation circuit 4, whereby digital two-phase square wave data OUTA and OUTB are obtained.
When intending to obtain a sufficient interpolation number in the interpolation circuit in which the look-up table memory is used as described above, capacity of the look-up table memory becomes extremely large. For example, when the digital data DA and DB obtained by A/D converters 2a and 2b are N bits, the size of the address space specified by the digital data DA and DB is N.times.N. When a required interpolation number is defined as I, the integer J beyond log.sub.2 I is required to the phase angle data. In such a condition, the memory capacity required in the look-up table memory becomes 2.sup.2N .times.J.
For example, the memory configuration where the phase angle data obtained by dividing one period into 400 are addressed with the address of 8 bits.times.8 bits becomes as FIG. 5. When a data length is defined as J=9, the memory capacity becomes 2.sup.8 .times.2.sup.8 .times.9=589,824 bits.
As a method for reducing the capacity of the look-up table memory in the encoder interpolation circuit of a digital system as described above, a method for reducing the address space have been proposed, paying attention to the symmetry that the phase angle data is repeated periodically within an address space with exception of a sign (Japanese Laid-open Patent Publication No.Hei.3-68812).